Field-effect transistors (FETs), in particular metal-oxide-semiconductor field-effect transistors (MOSFETs), have become increasingly popular for use in various power switching applications due to their inherent capability of switching at high frequencies (turn-on and off within 10 ns). Because of this high switching capability, power circuits that employ FET devices have been increasingly directed toward operation at high frequency. The main motivation for high frequency (f) operation is the reduction in size (proportional to 1/f) of passive components, such as transformers and filter capacitors, which can comprise a substantial proportion of volume of devices. Being able to switch a power semiconductor (FET) at a higher frequency allows one to take advantage of 1/f scaling of magnetics (due to lower flux density) and filters (since energy storage .alpha. CV.sup.2 f). For operation up to 1 MHz, the FET's performance is satisfactory; however, as the frequency is increased to 10 MHz and beyond, several factors limit its switching efficiency and safe operating area (SOA). The most critical limitation relates to the gate arrangement of FET arrays integrated onto a silicon wafer or die in electrical parallel fashion. For the majority of power FETs, the gate electrode is comprised of a polycrystalline silicon material that has an order of magnitude of higher resistivity than other metals, such as aluminum. The use of polycrystalline silicon is primarily selected because of its superior properties, including its ability to withstand high temperature and its ability to achieve a well-controlled electrical interface with silicon oxide.
Although the polycrystalline silicon has advantageous characteristics, the use of polycrystalline silcon for a gate electrode does suffer certain drawbacks which may be described with reference to FIG. 1 illustrating a prior art network 100. In FIG. 1, a plurality of polycrystalline gate electrodes are illustrated by a plurality of polysilicon resistor-MOS gate networks 102.sub.1, 102.sub.2, 102.sub.3 . . . 102.sub.N. As seen in FIG. 1, typically a gate signal 104 is distributed outward from a pad 106 centrally located within a die and by using an alluminum run, commonly referred to as a gate runner which has limitations for effectively reducing gate resistance. As used herein, the pad is a conductive area of an integrated circuit specially designed and positioned for interconnection to other circuit chips, with the pad being typically positioned around the periphery of the chip. The gate signal 104 propagates from the gate pad connection 106 and into the polysilicon resistor-MOS gate networks 102.sub.1, 102.sub.2, 102.sub.3 . . . 102.sub.N which act as delay lines. The delay encountered may be envisioned by the examination of the expression 108 of FIG. 1.
Consequently, during turn-on, the FET transistor represented by the polysilicon resistor-MOS gate networks 102.sub.1 . . . 102.sub.N closest to the gate pad 106 will turn on first, and the FET farthest away from the gate pad 106 with turn on last. This non-uniform turn-on has several disadvantages which increase as the operational frequency, f, increases, one of which is that the effective average-on resistance will be less than the static on-resistance. Another disadvantage, which is of more concern, is over stressing FETs closest to the gate pad 106 because they carry a larger share of the load current than those located further away from the gate pad 106. In addition, a similar situation occurs during turn-off when those FETs farthest away from the gate pad 106 are the last to turn-off, again resulting in an uneven distribution of current. For the arrangement of FIG. 1, under surge conditions, failures of the FETs occur, and such failures are usually seen as occurring near the gate pads.
To promote faster switching speeds, interconnection from one FET of the array to another FET of the array needs to be accomplished with a minimum of capacitive loading and a minimum of interconnect length, thus keeping the inductance of the interconnections low. Capacitive and inductance loading tend to slow down signal transmission such that high speeds cannot be maintained by FETs in communicating from each other. Although this is not a problem for the FETs in close proximity, it is for the others. The arrangement of FIG. 1 suffers from these limitations.
In addition, the gate resistance encountered when using a polycrystalline silicon gate electrode affects switching losses when a FET used for high power switching application is excited by a sinusoidal waveform. For such excitation, the gate switching loss is proportional to the gate resistance of the power FET, as well as to other resistances in the gate drive circuits. In conventional gate drive circuits, the other resistances include series interconnect resistances between driver devices and the main power FETs being driven by the driver. In order to switch at high frequencies, it is known to use sinusoidal (resonant) drive techniques so that the switching loss is proportional to the gate resistance instead of frequency. However, these techniques require the use of devices external to the FET chip which, in turn, adds to the inductance of the interconnection leads which, in turn, degrades the switching speed capability of the FET.
The efficiency of an FET is effected by conduction and switching contributors. In general, conduction losses are inversely related to the size (or resistance) of a power FET die, while gate switching losses are directly related to the size (or gate capacitance). Thus, balancing the losses between conduction and switching becomes a difficult task. In particular, as the switching frequency is increased, the use of larger devices to reduce conduction losses becomes counterproductive due to corresponding increases in switching losses that are proportional to the switching frequency. For any power circuit operating at a given switching frequency, there is an optimum FET size (resistance and capacitance) that minimizes power losses. However, this optimum FET size is not always easily achieved in practice because economics prevent a vendor from offering more than a few off-the-shelf FET dies, each having a given breakdown voltage and power level which determine the FET die size.
It is thus desirable that a FET and arrays thereof be provided that may be easily optimized for any given power level. It is further desirable to so optimize FETs and arrays thereof using the limited inventory of conventionally available FET dies.
Manufacturers have recently addressed the problem of uneven gate signal distributions, described with reference to FIG. 1, in various ways, e.g., by incorporating an extra level of metallization of gate runners, thereby reducing gate runner resistance. For relatively high voltage devices, a multiplicity of aluminum gate runners may typically be realized, but for relatively low voltage devices having limited topology, this multiplicity is not realizable. Although a reduction in gate runner resistance for relatively high voltage devices has advantageous effects, the extra level of metallization adds a burden to the device fabrication process.
In addition, additional circuits, such as current mirrors, have been incorporated into device packages to protect devices from lower switching speeds, but this added circuitry represents a costly increase.
High density interconnect (hDI) structures for integrated circuit packaging, as more fully described, for example, in U.S. Pat. Nos. 4,783,695 and 5,384,691, both of which are herein incorporated by reference, overcome some disadvantages of device element interconnections. HDI packaging utilizes metallization layers that provide excellent electrical conductivity for the interconnection of individual chips and, thus, substantially reduce the unwanted self-inductance and capacitive loading drawbacks caused by using leads to provide interchip and intrachip connections. Et is desirable to utilize the HDI techniques to free the off-the-shelf FET devices of their switching speed and performance limitations.
It is thus desirable to provide a FET array employing high density interconnect (HDU) techniques to reduce the effective resistance of polycrystalline silicon gate electrodes and to reduce the capacitive and inductance loading effects of interconnections, which limit the switching capabilities of the FET array, while at the same time providing a FET array free of the limitation of the degraded circuit performance due to the limited availability of various types of off-the-shelf FETs.